Conventionally, as recording media that can record and rewrite a large volume of data, memory devices employing a semiconductor, such as DRAMs or SRAMs, and rotating disk type recording media, such as hard disks, magnetic optical disks or an optical disks, have been available. Systems employing any one of the recording media have been developed and used. Among these recording media, DRAMs, which are characterized by, e.g., fast writing and reading speed of data and easy high integration, have been broadly employed as a main memory device for a personal computer. However, because DRAMs have volatility characteristic (that is, stored data are lost when power supply from an external power source is stopped) that is fatal to a memory, the DRAMs have caused, e.g., problems that it takes much time to start up a personal computer employing a DRAM, and that prepared data are lost by, e.g., a sudden stop of power supply or failure to store the data.
On the other hand, although hard disk systems do not have volatility characteristic of data, these systems have caused problems of slow writing and reading speed and relatively high power consumption. For such reasons, the advent of a memory has been expected, which has characteristics, e.g., convenience in use, such as fast writing and reading speed, low power consumption, and non-volatility.
As memories that satisfy the above requirements, nonvolatile semiconductor memory devices, such as flash memory, ferroelectric memory, MRAM (Magnetic Random Access Memory) and phase change memory, have been expected and been under development.
Each of the memories have both advantages and disadvantages. For example, MRAM has lots of merits, such as fast writing speed and an excellent endurance, therefore it has been said to be one of the leading candidates as replacements for DRAM. However, since MRAM cell composes a transistor and a TMR (Tunnel Magneto Resistive) element, which makes disadvantageous in manufacturing cost due to its relatively complicated cell structure, and MRAM also has to employ a ferromagnetic material involving many technical problems in terms of process. And, more importantly, there is a problem that the manufacturing technology for TMR element with minimized dispersions in characteristics is difficult to be established.
On the other hand, flash memory can have a cell size reduced due to its simple structure with one transistor basically. Additionally, highly integrated flash memory can be relatively inexpensively produced by employing a conventional DRAM technology. For such reasons, attention has been drawn to flash memory as a frontrunner in several nonvolatile memories for a personal digital assistant (mobile information device). Recently, it has been promoted to operate semiconductor devices faster and to fabricate semiconductor devices in high integration. Being affected by this trend, research has actively conducted for providing flash memory with high performance, such as fast operation, miniaturization or an improved charge retention ability.
When NOR flash memory are given as an example of currently dominant floating-gate type flash memory, reading of stored data from a designated memory cell is rapidly carried out in a relatively short time of about 100 ns (nanosecond) or less. NOR flash memory have more than a half share in the flash memory market, for being used for storing, e.g., a program code of a mobile information device.
On the other hand, a data is written by hot electron injection from a channel to a floating gate. And, a data is erased by discharge due to a Fowler-Nordheim tunneling current from the floating gate to a channel forming region or to a source. The hot electron injection is fast in terms of charge transfer speed, but low in terms of charge injection efficiency (proportion of an injecting current to a supply current). And then the Fowler-Nordheim tunneling current at discharging is high in terms of the charge injection efficiency, but slow in terms of the charge transfer speed. Consequently, both require much time for rewriting.
Specifically, it takes a relatively long time on the order of 1 μs (microsecond) for writing and on the order of from several hundreds of ms (millisecond) to several seconds (second) for erasing. For this reason, it has been difficult to replace high-speed memory, such as DRAM, by flash memory, since, although flash memory are relatively easy to increase capacity and reduce costs, the application of the flash memory is limited.
In order to shorten the writing time to overcome such a drawback, for example, it is proposed to reduce the physical thickness of an oxide film which is the tunnel insulating film of a memory cell. However, if the thickness is reduced, dielectric breakdown (stress-induced leakage current) of the oxide film is likely to be caused by a stress, which is caused by charges passing many times through the oxide film due to repeated rewriting since the tunnel oxide film is subjected to a very strong electric field in inverse proportion to the thickness when the floating gate is electrically charged.
If dielectric breakdown occurs even at one location in a tunnel oxide film, most amount of charges retained in the floating gate leaks out, and the memory cell loses data retention ability afterward. This makes it difficult to improve the endurance characteristic of flash memory. Therefore, since there is not other choice but to form the tunnel oxide film to be as thick as about 10 nm in order to obtain the reliability of charge retention, it is difficult to shorten the time of rewriting under the present circumstances. Additionally, since the dimensions of the oxide film thickness and the entire cell have to be shrunk similarly, miniaturization of the entire cell size is also hampered.
As means for preventing the charge retention ability from being lowered by dielectric breakdown while maintaining high speed performance, there is a method for retaining charges in a spatially discrete manner. As a nonvolatile semiconductor memory employing such a method, there is MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor). An example of conventional MONOS memory is shown in FIG. 3. The shown MONOS memory has such a structure that a SiNx film 5, instead of the floating gate, is stacked upon a tunnel insulating film 2 as shown in FIG. 3. The MONOS memory is a memory which retains charges in interface levels 4a existing at the interfaces and in trap levels 4b discretely distributed in the SiNx film 5. Additionally, in FIG. 3, reference numeral 1 designates a p-type single crystal Si substrate, reference numeral 4 is a charge retention region, reference numeral 6 designates a gate insulating film, reference numeral 7 designates a control gate, reference numeral 9 designates a source region, reference numeral 10 designates a drain region, and reference numeral 11 designates a channel forming region.
Since the interface levels 4a and the trap levels 4b, which retain charges, are distributed in a spatially discrete manner, charge leakage only occurs locally even if dielectric breakdown is caused at a location in the tunnel insulating film. Hence, the charge retention ability of the memory cell does not change significantly before and after occurrence of the dielectric breakdown.
For such reasons, MONOS memory is more excellent than the floating-gate-type flash memory in terms of the endurance and is regarded as being advantageous in terms of miniaturization or the like of the memory cells since the physical thickness of the tunnel insulating films can be made relatively thin. However, for, e.g., the reason why the depth of the trap levels of the SiNx film (the energy difference between the trap level and the bottom of the conduction band for electrons, and the energy difference between the trap level and the top of the valence band for holes) is not necessarily enough, a charges that are once trapped is likely to escape, therefore MONOS memory is disadvantageous in that the absolute charge retention ability (the charge retention ability of a device, which is in a normal state and is subjected to no dielectric breakdown) is low.
On the other hand, as a method for dealing with the dielectric breakdown of the oxide film by retaining charges in a discrete manner as in MONOS memory and for further enhancing the absolute charge retention ability than the MONOS memory, a structure wherein floating gate is replaced by a plurality of nano-particles and the nano-particles are dispersed in the gate insulating film, has been considered. In FIG. 4, an example of semiconductor memory devices wherein nano-particles are formed from Si nano-particles is shown as a typical device having this structure. The same reference numerals as the elements in FIG. 3 indicate the same elements except for an charge retention region 4 in FIG. 4. A memory having this structure is disclosed in, e.g., JP-A-11-186421. This publication discloses a structure wherein a floating gate 4, which comprises a group of a plurality of Si nano-particle formed by a CVD method, is formed on a tunnel insulating film 2, and wherein the floating gate is covered with a gate insulating film 6.
However, the currently available Si nano-particles have a size of from about 5 to about 10 nm and an in-plane distribution density (area density) of from 1 to 2×1012/cm2, and these values are insufficient in terms of memory function.
When the area density of nano-particles that function as a charge retention part is low, the memory window (the shift width of threshold voltage in a MOS transistor) of the flash memory is narrowed since the area density of the amount of retained charges is also lowered. At the same time, dispersion in the area density of the amount of charges among semiconductor memory cells, are likely to be relatively large, which has an adverse influence on dispersion in the size of the memory window. Both phenomena make data reading operation unstable.
Therefore, it is necessary to increase the area density while ensuring a distance among nano-particles and maintaining a discrete state. However, in the formation by the CVD method disclosed in JP-A-11-186421, when a manufacturing condition is changed in order to increase the area density of the nano-particles, the nano-particles cannot be formed with a sufficient area density since adjacent nano-particles are likely to agglomerate and since the discrete state cannot be maintained.
Further, recently, a research on single-electron memory, which is ultrafast and extremely low power consumption memory, has been actively carried out. As one of the conditions to realize single-electron memory, it is necessary to exhibit the Coulomb blockade effect (wherein energy barriers that restrain surrounding electrons from approaching are generated by the electrostatic potential field of accumulated electrons, and further, the electrons are prevented from moving beyond the energy barriers in the sense of statistical thermodynamics since the energy barriers have a higher level than the thermal energy of the electrons) at room temperature. In order to exhibit this effect, it is essential that the size of the floating gate 4 be decreased.
In order for single-electron memory to stably functions at room temperature, it is said that the size of the floating gate 4 has to be reduced to have a diameter of about 1 nm. However, the smallest particle size of currently available nano-particles has remained at about 5 nm. Since it is necessary for at least one nano-particle to be formed in the gate region of a quite miniaturized single-electron memory with a high probability, it is required to have a high nano-particles formation density. From this viewpoint, the currently available area density of about 1012/cm2 is insufficient. Further, in order to accomplish such the area density, a quite peculiar pre-treatment is necessary which causes a problem of making the fabrication process complicate.
It is an object of the present invention to provide a nonvolatile semiconductor memory device having a structure that is capable of solving the problems to be overcome in the conventional flash memory, specifically, is capable of reducing the time required for writing and erasing operation and preventing charge retention characteristic from being deteriorated by repetition of rewriting operation, and to provide a process for producing the nonvolatile semiconductor memory device with good reproducibility.